1. Enter debug interface mode.
2. Enable reset through the RESET register in the POWER peripheral.
3. Hold the SWDCLK and SWDIO/nRESET line low for a minimum of 100 μs.
The DIF module will be in normal mode after power on reset. In this mode the SWDIO/nRESET pin acts as a normal active low reset pin. To guarantee that the device remains in normal mode, the SWDCLK line must be held low, that is, '0', at all times. Failing to do so may result in the DIF entering into an unknown state and may lead to undesirable behavior and power consumption.
The first part, 0x95, is the command sent by the host. What this command says is the following: 0x95 is the same as 0xb1001 0101.(0xb 1010 1001) From the command description above, you can see that this translates into: Start(1), APnDP(0 – Debug Port), RnW(0 – write), A2:3, Parity(1), Stop(0), Park(1). This means, write to Debug Port, address 0b0100, the value that follows which is 0x00000000. The address is then defined by the DPBANKSEL register – which should be 0 for the exit debug mode command. Address 0x0100 (0x4 of the DP) is as seen above the CTRL/STAT register. Writing 0x0 to this register will clear all Debug resource requests and thus exit Debug Mode.
CPU System Reset hold and run
This sequence describes how to do a system reset with hold, then run.
For more information on:
• DAP, see the ADI v5.1 version of the ARM Debug Interface v5, Architecture Specification
• CoreSight DAP, see the ARM CoreSight Components Technical Reference Manual.
10.1.2 Debug interface mode
Debug interface mode is initiated by clocking one clock cycle on SWDCLK with SWDIO=1. Due to delays caused by starting up the DAP's power domain, a minimum of 150 clock cycles must be clocked at a speed of minimum 125 kHz on SWDCLK with SWDIO=1 to guaranty that the DAP is able to capture a minimum of 50 clock cycles.
Exit Debug Mode
In order to exit debug mode, write the following command with DP.SELECT address bank set to 0:
0x95 0x00000000 // Clear PWRUP Request to CTRL/STAT0xb1001 0101.(0xb 1010 1001)
Exit Debug Mode
In order to exit debug mode, write the following command with DP.SELECT address bank set to 0:
0x95 0x00000000 // Clear PWRUP Request to CTRL/STAT0xb1001 0101.(0xb 1010 1001)
The first part, 0x95, is the command sent by the host. What this command says is the following: 0x95 is the same as 0xb1001 0101.(0xb 1010 1001) From the command description above, you can see that this translates into: Start(1), APnDP(0 – Debug Port), RnW(0 – write), A2:3, Parity(1), Stop(0), Park(1). This means, write to Debug Port, address 0b0100, the value that follows which is 0x00000000. The address is then defined by the DPBANKSEL register – which should be 0 for the exit debug mode command. Address 0x0100 (0x4 of the DP) is as seen above the CTRL/STAT register. Writing 0x0 to this register will clear all Debug resource requests and thus exit Debug Mode.
CPU System Reset hold and run
This sequence describes how to do a system reset with hold, then run.
(實作測試，下列swd序列可以讓nrf51822 mcu reset 離開debug mode並進入normal mode)
For more information on:
• DAP, see the ADI v5.1 version of the ARM Debug Interface v5, Architecture Specification
• CoreSight DAP, see the ARM CoreSight Components Technical Reference Manual.
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